Matches 401 - 450 out of 17410 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >
Match Document Document Title
7382408 Varying capacitance that receives signals from sensing elements  
Capacitance on a readout line is varied while receiving a signal, from a light sensing pixel or other sensing element through the line. Capacitance can be varied in accordance with a readout...
7382407 High intrascene dynamic range NTSC and PAL imager  
The invention provides a new method and apparatus for NTSC and PAL image sensors which employs fusion of adjacent row pixel charge samples to generate image data for a row. A variety of fusion...
7382227 Portable computer supporting paging instructions  
A portable computer is described that contains a circuit for receiving pages and performing security functions based on the received page. Once a page has been received by the portable computer,...
7382177 Voltage charge pump and method of operating the same  
A voltage pump comprising a charging transistor responsive to a first control signal, the charging transistor operable to connect a node to a first voltage, a pumping capacitor responsive to a...
7382060 Semiconductor component having thinned die, polymer layers, contacts on opposing sides, and conductive vias connecting the contacts  
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit...
7381647 Methods and systems for planarizing microelectronic devices with Ge-Se-Ag layers  
Microelectronic devices including a layer of germanium and selenium, optionally including up to 10 atomic percent silver, show promise for select applications. Manufacturing microelectronic devices...
7381591 Flip-chip adaptor package for bare die  
A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead...
7381573 Self-aligned, low-resistance, efficient memory array  
The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor...
7380328 Method of forming an inductor  
The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns...
7379382 System and method for controlling timing of output signals  
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs...
7379377 Memory array decoder  
An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location...
7379365 Method and apparatus for charging large capacitances  
A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator compares a reference voltage to a...
7379336 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7379315 Apparatus and methods for optically-coupled memory systems  
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and...
7379068 Memory system and method for improved utilization of read and write bandwidth of a graphics processing system  
A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory...
7378891 Measure-controlled circuit with frequency control  
Some embodiments include a delay locked circuit having multiple paths. A first path measures a timing of a first clock signal during a measurement. A second path generates a second clock signal...
7378737 Structures and methods to enhance copper metallization  
Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary...
7378736 Ball grid array structures having tape-based circuitry  
Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape...
7378723 Method and apparatus for decoupling conductive portions of a microelectronic device package  
A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic substrate and a conductive member...
7378719 Low leakage MIM capacitor  
Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between...
7378707 Scalable high density non-volatile memory cells in a contactless memory array  
A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and...
7378704 Semiconductor constructions, and methods of forming semiconductor constructions  
The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at...
7378697 Pinned photodiode structure and method of formation  
An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack...
7378696 Pinned photodiode structure and method of formation  
An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack...
7378635 Method and apparatus for dark current and hot pixel reduction in active pixel image sensors  
A method of operating an imager pixel that includes the act of applying a relatively small voltage on the gate of a transfer transistor during a charge acquisition period. If a small positive...
7378354 Atomic layer deposition methods  
The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic...
7378353 High selectivity BPSG to TEOS etchant  
An organic acid/fluoride-containing solution etchant having high selectivity for BPSG to TEOS. In an exemplary situation, a TEOS layer may be used to prevent contamination of other components in a...
7378342 Methods for forming vias varying lateral dimensions  
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are...
7378316 Method for fabricating semiconductor vertical NROM memory cells  
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer...
7378313 Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules  
Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an...
7378311 Method of forming memory cells in an array  
The invention includes a 6F 2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first...
7378290 Isolation circuit  
An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is...
7378199 Micro-lenses and method for increasing area coverage and controlling shape of micro lenses  
Micro-lenses for use in imagers and their method of manufacture from intermediate lens structures are described. Lithographic masks are used to remove unwanted portions from the intermediate lens...
7378129 Atomic layer deposition methods of forming conductive metal nitride comprising layers  
This invention includes atomic layer deposition methods of forming conductive metal nitride comprising layers. In one implementation, an atomic layer deposition method of forming a conductive metal...
7378127 Chemical vapor deposition methods  
A chemical vapor deposition apparatus includes a deposition chamber defined at least in part by chamber walls, a substrate holder inside the chamber, and at least one process chemical inlet to the...
7377018 Method of replacing a subpad of a polishing apparatus  
A subpad support for use in a web format or belt format polishing apparatus for polishing one or more layers of semiconductor device structures. The subpad support includes a subpad retention...
7376874 Method of controlling a test mode of a circuit  
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test...
7376857 Method of timing calibration using slower data rate pattern  
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than...
7376669 System for automatically initiating a computer security and/or screen saver mode  
A system for automatically switching a computer to a password protected screen saver mode when a computer user leaves the proximity of the computer. The system includes a proximity sensor that...
7376244 Imaging surveillance system and method for event detection in low illumination  
A surveillance system and method is provided for detecting and event and then capturing an image of the event under low illumination conditions. A camera captures a current image and a prior...
7376025 Method and apparatus for semiconductor device repair with reduced number of programmable elements  
An apparatus and method using a reduced number of fuses for enabling redundant memory blocks in a semiconductor memory is disclosed. In one embodiment, a redundancy selection module may be...
7376024 User configurable commands for flash memory  
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of the initialization routine. If the...
7375892 Ellipsoidal gapless microlens array and method of fabrication  
Ellipse-shaped microlenses focus light onto unbalanced photosensitive areas, increase area coverage for a gapless layout of microlenses, and allow pair-wise or other individual shifts of the...
7375793 Apparatus for photolithographic processing  
Photolithographic processing apparatus and methods are disclosed. In one embodiment, a method of photolithographically patterning a surface of a substrate includes forming a photoreactive layer on...
7375748 Differential readout from pixels in CMOS sensor  
The present invention provides an improved pixel readout circuit that compensates for common mode noise during a read out operation. This is accomplished by using a differential readout of the...
7375573 De-emphasis system and method for coupling digital signals through capacitively loaded lines  
A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a...
7375560 Method and apparatus for timing domain crossing  
A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The...
7375554 Voltage level translator circuitry  
Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage protection circuitry to ensure that...
7375419 Stacked mass storage flash memory package  
A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the...
7375414 High permeability layered films to reduce noise in high speed interconnects  
This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated...
Matches 401 - 450 out of 17410 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >