Matches 301 - 350 out of 17370 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7388801 Reduction of fusible links and associated circuitry on memory dies  
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses....
7388794 Individual I/O modulation in memory devices  
A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their...
7388789 NAND memory device and programming methods  
A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled together to charge share their...
7388779 Multiple level programming in a non-volatile device  
The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The...
7388608 Sample and hold circuit and active pixel sensor array sampling system utilizing same  
An active pixel sensor array sampling system includes a plurality of video circuits and reset circuits. A video circuit generates a video voltage from each one of the pixels of a column of pixels....
7388462 Integrated circuit inductors  
The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is increased through the use of...
7388391 Method for evaluating at least one electrical conducting structure of an electronic component  
An apparatus and method for evaluating the integrity of each contact pin of an electronic component having multiple contact pins. In one embodiment, the apparatus includes a test device and a...
7388294 Semiconductor components having stacked dice  
A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary...
7388290 Spacer patterned, high dielectric constant capacitor and methods for fabricating the same  
A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer...
7388289 Local multilayered metallization  
An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth, and the number of metal layers is a...
7388251 Non-planar flash memory array with shielded floating gates on silicon mesas  
A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the...
7388248 Dielectric relaxation memory  
A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy...
7388246 Lanthanide doped TiOx dielectric films  
A dielectric film containing lanthanide doped TiO x and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than...
7388241 Pinned photodiode structure and method of formation  
An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface layer, self-aligned to a gate stack...
7388239 Frame shutter pixel with an isolated storage node  
A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.
7388183 Low dark current pixel with a guard drive active photodiode  
A method and apparatus for reducing thermally generated dark current in a CMOS imaging device is disclosed. A photodiode within the imaging device is kept zero-biased, so that the voltage is equal...
7387959 Method of fabricating integrated circuitry  
The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then,...
7387940 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry  
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated...
7387939 Methods of forming semiconductor structures and capacitor devices  
The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive...
7387912 Packaging of electronic chips with air-bridge structures  
A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A...
7387909 Methods of forming assemblies displaying differential negative resistance  
The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at least about 9. The invention also...
7387908 CMOS imager with enhanced transfer of charge and low voltage operation and method of formation  
A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are...
7387902 Methods for packaging image sensitive electronic devices  
The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the...
7387866 Photolithography process using multiple anti-reflective coatings  
A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another...
7387853 Use of a planarizing layer to improve multilayer performance in ultraviolet masks  
The present invention relates to fabricating a reticle or mask for use in an extreme ultraviolet (“EUV”) photolithographic process. The EUV reticle comprises a substrate, a planarizing layer...
7387685 Apparatus and method for depositing materials onto microelectronic workpieces  
Reactors for vapor deposition of materials onto a microelectronic workpiece, systems that include such reactors, and methods for depositing materials onto microelectronic workpieces. In one...
7387119 Dicing saw with variable indexing capability  
A saw for dicing substrates, such as semiconductor wafers, that has one or more variable indexing capabilities and two or more blades. One of the blades may be moved laterally or vertically,...
7386689 Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner  
A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal...
7386660 CAM with automatic writing to the next free address  
A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid locations are determined...
7386657 Random access interface in a serial memory device  
A random access interface is provided to a non-volatile, serial memory array. An address multiplexer has an external address connection and a serial address connection. The external address may be...
7386649 Multiple processor system and method including multiple memory hub modules  
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and...
7386186 Apparatus and method for processing images  
A method and apparatus for processing an image. Specifically, one exemplary embodiment of the method comprises inputting an image into a pixel array producing pixel output signals, executing an...
7385871 Apparatus for memory device wordline  
A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of...
7385868 Method of refreshing a PCRAM memory device  
A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require separate control and application of...
7385846 Reduction of adjacent floating gate data pattern sensitivity  
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account...
7385842 Magnetic memory having synthetic antiferromagnetic pinned layer  
A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel barrier on a side opposite the sense...
7385547 Minimized differential SAR-type column-wide ADC for CMOS image sensors  
An analog-to-digital converter comprising a minimal amount of circuitry for conversion of an input analog signal to a series of digital bits. A differential comparator is provided for generating...
7385412 Systems and methods for testing microfeature devices  
Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate...
7385298 Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same  
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a...
7385290 Electrochemical reaction cell for a combined barrier layer and seed layer  
Methods and apparatus for forming conductive interconnect layers useful in articles such as semiconductor chips, memory devices, semiconductor dies, circuit modules, and electronic systems. An...
7385259 Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device  
A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered...
7385245 Low power memory subsystem with progressive non-volatility  
The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge...
7385240 Storage cell capacitor compatible with high dielectric constant materials  
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an...
7385238 Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors  
A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the...
7385232 CMOS imager with enhanced transfer of charge and low voltage operation and method of formation  
A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are...
7385222 Thin film transistors and semiconductor constructions  
A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material...
7385167 CMOS front end process compatible low stress light shield  
An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding and light-transparent material. The...
7385166 In-pixel kTC noise suppression using circuit techniques  
A circuit and method for reducing kTC noise in CMOS imagers while minimizing power dissipation is disclosed. Correlated double sampling (CDS) is performed within each pixel such that the reset...
7384849 Methods of forming recessed access devices associated with semiconductor constructions  
The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are...
7384847 Methods of forming DRAM arrays  
The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering...
Matches 301 - 350 out of 17370 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >