Matches 101 - 150 out of 17311 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7406216 Method and apparatus for distributed analyses of images  
A method and apparatus for intelligent distributed analyses of images including capturing the images and analyzing the captured images, where feature information is extracted from the captured...
7405966 Magnetic tunneling junction antifuse device  
An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft...
7405552 Semiconductor temperature sensor with high sensitivity  
An temperature sensor circuit is disclosed. In one embodiment, the temperature sensor comprises an input circuit with a current mirror for forcing a current down a reference stage and an output...
7405487 Method and apparatus for removing encapsulating material from a packaged microelectronic device  
A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at least partially surrounds a...
7405463 Gate dielectric antifuse circuit to protect a high-voltage transistor  
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric...
7405455 Semiconductor constructions and transistor gates  
One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and...
7405454 Electronic apparatus with deposited dielectric layers  
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using...
7405447 Silicon rich barrier layers for integrated circuit devices  
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to...
7405444 Micro-mechanically strained semiconductor film  
A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process including performing a local...
7405438 Capacitor constructions and semiconductor structures  
The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the...
7405385 Micro-lens configuration for small lens focusing in digital imaging devices  
An improved image sensor wherein a first micro-lens array comprised of one or more micro-lenses is positioned over a cavity such that incoming light is focused on the photo sensors of the image...
7405110 Methods of forming implant regions relative to transistor gates  
The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is...
7405101 CMOS imager with selectively silicided gate  
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The...
7405007 Semiconductor having a substantially uniform layer of electroplated metal  
A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of the applied potential or current...
7404162 Buffering technique using structured delay skewing  
A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design...
7404124 On-chip sampling circuit and method  
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the...
7404071 Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices  
Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of...
7404066 Active memory command engine and method  
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array...
7404033 Method for reading while writing to a single partition flash memory  
A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient time available to perform the...
7403444 Selectable memory word line deactivation  
Circuitry and methods allow selected memory word lines (WLs) to be deactivated without using a global deactivate signal. All active WLs do not therefore have to be deactivated simultaneously, which...
7403425 Programming a flash memory device  
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is...
7403423 Sensing scheme for low-voltage flash memory  
Single-ended sensing devices for sensing a programmed state of a non-volatile memory cell are adapted for use in low-voltage memory devices. Methods of their operation include precharging an input...
7403419 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7403416 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7403060 Forward biasing protection circuit  
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body terminal of the transistor, and a...
7403044 Method of producing balanced data output  
Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP...
7403033 MOS linear region impedance curvature correction  
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in...
7402908 Intermediate semiconductor device structures  
A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive, insulative material. A conformed metal layer...
7402902 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice  
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board,...
7402879 Layered magnetic structures having improved surface planarity for bit material deposition  
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and...
7402876 Zr— Sn—Ti—O films  
A dielectric film containing Zr—Sn—Ti—O formed by atomic layer deposition using a TiI 4 precursor and a method of fabricating such a dielectric film produce a reliable dielectric layer...
7402861 Memory cells and select gates of NAND memory arrays  
A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric layer. Conductive spacers are...
7402850 Back-side trapped non-volatile memory device  
Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of...
7402833 Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication  
A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer...
7402789 Methods for pixel binning in an image sensor  
Embodiments provide structures and methods for binning pixel signals of a pixel array. Pixel signals for pixels in an element of the array are binned simultaneously. Pixels in an element are...
7402533 Masking without photolithography during the formation of a semiconductor device  
A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely spaced regions, such as a memory transistor array, and...
7402526 Plasma processing, deposition, and ALD methods  
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least...
7402518 Atomic layer deposition methods  
A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor...
7402516 Method for making integrated circuits  
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or...
7402512 High aspect ratio contact structure with reduced silicon consumption  
A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening...
7402498 Methods of forming trench isolation regions  
The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one...
7402489 Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same  
A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation...
7402453 Microelectronic imaging units and methods of manufacturing microelectronic imaging units  
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a...
7402451 Optimized transistor for imager device  
An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area...
7402379 Resist exposure system and method of forming a pattern on a resist  
A resist exposure system and a method of forming a pattern on a resist are provided and include an exposure source, a photoresist composition, and a mask positioned therebetween. The resist...
7402259 Chemical-mechanical polishing methods  
A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion of the abrasive material, and...
7402094 Fixed-abrasive chemical-mechanical planarization of titanium nitride  
Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an...
7401267 Program failure recovery  
Methods and apparatus are provided. A method of operating a memory device includes detecting a programming failure at a first location of a memory array, preserving data within the memory device...
7401010 Methods of forming radiation-patterning tools; carrier waves and computer readable media  
The invention includes a method for placement of sidelobe inhibitors on a radiation-patterning tool. Elements of the tool are represented by design features in a modeling domain. The modeling...
7400549 Memory block reallocation in a flash memory device  
A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that...
Matches 101 - 150 out of 17311 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >