Matches 701 - 750 out of 17370 < 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 >
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7341906 Method of manufacturing sidewall spacers on a memory device, and device comprising same  
The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment,...
7341901 Semiconductor processing methods of forming integrated circuitry  
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry...
7341881 Methods of packaging and testing microelectronic imaging devices  
Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die...
7341502 Methods and systems for planarizing workpieces, e.g., microelectronic workpieces  
Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a planarizing condition. This process...
RE40137 Methods for forming integrated circuits within substrates  
The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of forming an integrated circuit within a...
7340668 Low power cost-effective ECC memory system and method  
A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from...
7340584 Sequential nibble burst ordering for data  
A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode...
7339839 Triggering of IO equilibrating ending signal with firing of column access signal  
A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a...
7339838 Method and apparatus for supplementary command bus  
An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates...
7339830 One transistor SOI non-volatile random access memory cell  
Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried insulator, first and second source/drain...
7339818 Spintronic devices with integrated transistors  
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and...
7339812 Stacked 1T-nmemory cell structure  
This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time...
7339811 Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation  
This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher...
7339431 CMOS amplifiers with frequency compensating capacitors  
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the...
7339423 Technique to improve the gain and signal to noise ratio in CMOS switched capacitor amplifiers  
The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using...
7339408 Generating multi-phase clock signals using hierarchical delays  
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that...
7339239 Vertical NROM NAND flash memory array  
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of...
7339228 Non-planar flash memory array with shielded floating gates on silicon mesas  
A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the...
7339217 High dynamic range image sensor  
A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a dual purpose, acting as both a...
7339191 Capacitors having doped aluminum oxide dielectrics  
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques...
7338889 Method of improving copper interconnects of semiconductor devices for bonding  
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a...
7338866 Strapping word lines of NAND memory devices  
Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first portions of first word lines of a...
7338856 Double-doped polysilicon floating gate  
The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on...
7338851 Diode/superionic conductor/polymer memory structure  
A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over...
7338609 Partial edge bead removal to allow improved grounding during e-beam mask writing  
A method to provide a ground point for second, or subsequent, e-beam mask-writing steps by selectively removing the photoresist edge bead of a photomask substrate to expose the underlying chrome...
RE40114 Tungsten silicide (WSIX) deposition process for semiconductor manufacture  
A semiconductor manufacturing process for depositing a tungsten silicide film on a substrate includes deposition of a tungsten silicide nucleation layer on the substrate using a (CVD) process with...
7337404 Graphical representation of system information on a remote computer  
A method and apparatus for gathering system information into a file and transmitting the file to a remote location for presentation as a graphical display. A computerized diagnostic tool, can...
7337088 Intelligent measurement modular semiconductor parametric test system  
An intelligent measurement modular semiconductor parametric test system comprises an engine control module. The engine control module is operable to communicate with a user via a user interface,...
7336548 Clock generating circuit with multiple modes of operation  
A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A...
7336547 Memory device having conditioning output data  
A memory device has a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data. During a memory operation, the...
7336541 NAND flash memory cell programming  
A flash memory device, such as a NAND flash, is included having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply...
7336537 Handling defective memory blocks of NAND memory devices  
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively...
7336536 Handling defective memory blocks of NAND memory devices  
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively...
7336531 Multiple level cell memory device with single bit per cell, re-mappable memory block  
A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One...
7336522 Apparatus and method to reduce undesirable effects caused by a fault in a memory device  
A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline...
7336430 Extended depth of field using a multi-focal length lens with a controlled range of spherical aberration and a centrally obscured aperture  
An extended depth of field is achieved by a computational imaging system that combines a multifocal imaging subsystem for producing a purposefully blurred intermediate image with a digital...
7336111 Fast-locking digital phase locked loop  
An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop...
7336106 Phase detector and method having hysteresis characteristics  
A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the...
7336084 Delay lock circuit having self-calibrating loop  
A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement to obtain a measured delay. The...
7335994 Semiconductor component having multiple stacked dice  
A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary...
7335988 Use of palladium in IC manufacturing with conductive polymer bump  
An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a...
7335985 Method and system for electrically coupling a chip to chip package  
A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals....
7335981 Methods for creating electrophoretically insulated vias in semiconductive substrates  
Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting...
7335978 Semiconductor component having stiffener, circuit decal and terminal contacts  
A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as...
7335968 High permeability composite films to reduce noise in high speed interconnects  
A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first layer of electrically conductive...
7335965 Packaging of electronic chips with air-bridge structures  
A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A...
7335963 Light block for pixel arrays  
Imager devices are formed with light block material between microlenses to enhance the characteristics of image acquisition. The light block material may be deposited over the lenses, and then...
7335962 Photonic crystal-based lens elements for use in an image sensor  
The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a substrate and a plurality of...
7335958 Tailoring gate work-function in image sensors  
Embodiments of the invention provide a method of forming a pixel cell and the resultant pixel cell a photo-conversion device formed at a surface of a substrate and a transistor adjacent to the...
7335935 Semiconductor structures  
Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure...
Matches 701 - 750 out of 17370 < 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 >